1. Field of the Invention
This invention relates to electrically erasable programmable read-only memory (EEPROM) cells, and more particularly to byte-erasable ("full-featured") EEPROM cells.
2. Description of the Prior Art
With conventional byte-erasable EEPROM cells a problem exists in that conventional prior art byte-erasable cells require a high external voltage source to program and erase a floating gate.
A typical prior art byte-erasable EEPROM cell has been described in an article entitled "A High Density Floating Gate EEPROM Cell" by John R. Yeargain et al., which appeared in IEDM, 1981. (Note that the erase/program convention of the article is the reverse of the description prior art EEPROM cell, below.)
FIG. 1 illustrates in simplified and greatly enlarged fashion a typical prior art byte-erasable EEPROM cell such as the described in the above-referenced article. The EEPROM cell contains a select transistor in series with a floating-gate memory transistor. Referring to FIG. 1, cell 1, shown in side view, is comprised of substrate 5 of semiconductor material having a P-type dopant. Formed in the upper surface 6 of substrate 5 is a first drain region 7a, a second drain region 7b and a source region 8, all made of highly doped N-type material. Channel region 9a extends between first and second drain regions 7a, 7b, and channel region 9b extends between adjacent edges of source region 8 and second drain region 7b. Upon surface 6 of substrate 5 is a first insulating layer 10, which may typically be silicon dioxide, first insulating layer 10 forming what is known as a gate oxide. The first insulating layer 10 has a thickness of approximately 200 .ANG.. Formed over first insulating layer 10 are floating gate 2 and select gate 4, both typically composed of polycrystalline silicon (polysilicon). As will be appreciated by reference to FIG. 1, select gate is positioned over first channel region 9a and floating gate 2 is positioned over second channel region 9b. Select gate 4 has one edge overlapping first drain region 7a and another edge overlapping second drain region 7b. Floating gate 2 has one edge overlapping a portion of second drain region 7b and another edge overlapping source region 8. Formed over floating gate 2 is a second insulating layer 11, typically composed of polysilicon oxide. Control gate 3 is positioned over channel 9b and substantially rests on second insulating layer 11. Control gate 3 has one depending portion which overlaps a portion of source region 8 and a second depending portion which overlaps a portion of second drain region 7b, with the middle portion of control gate 3 disposed over floating gate 2.
In erasing cell 1, control gate 3 is grounded and approximately 20 volts is applied to the select transistor 4 and the first drain region 7a. The source region 8 is biased to approximately 5-10 volts. Under these conditions, erasing is accomplished by the tunneling of electrons from the floating gate 2 through the first insulating layer 10 in response to the high applied drain voltage. This manner of erasing is known in the art as Fowler-Nordheim tunneling.
Programming is also accomplished by Fowler-Nordheim tunneling. In programming cell 1, source region 8, second drain region 7b and substrate 5 are grounded and a reversible voltage of approximately 20 volts is applied to the select gate and the control gate 3. Under these conditions, electrons tunnel from the source region 8, second drain region 7b and substrate 5 through the first insulating layer 10 to the floating gate 2.
During a read function a potential of 5 volts is applied to the select transistor 4 and a voltage of 1 volt is applied to the second drain region 7b. Both the control gate 3 and the source region 8 are grounded. If a net positive charge exists in the floating gate 2 (i.e., an erase function has been performed on the floating gate) then the floating gate 2 will allow a current to flow through the channel 9 between the source region 8 and the second drain region 7b.
A problem with the prior art byte erasable EEPROM cell is that a high external voltage source is required for the erase and program function. To provide high voltages on a memory chip while using only a 5 volt external source, it is known in the art to use a voltage multiplier. However, if a voltage multiplier is used on the prior art byte-erasable EEPROM cell discussed above, a gate-modulated junction breakdown effect will cause the voltage multiplier to collapse. Gate-modulated junction breakdown occurs when electrons are drawn from the channel region surrounding the drain in response to the electric field generated by the floating gate. The large number of electrons drawn into the drain region from the channel region results in a high current flow. Because a voltage multiplier requires a low current to create a desired high voltage, the high current generated by the gate-modulated junction breakdown causes the voltage multiplier to collapse, causing failure of the cell.
In addition, the use of a voltage multiplier on the prior art byte-erasable EEPROM cell will limit the erased cell threshold voltage. The erased cell threshold voltage is the voltage level of the floating gate at which the channel is "turned on"; that is, enough current is allowed through the channel to sense the "erased" state of the floating gate. If the channel is "turned on" during an erase function (i.e., when enough electrons tunnel out of the floating gate to give it a net positive charge equal to the threshold voltage), then the additional DC current across the channel can collapse the voltage multiplier. This limits the erased cell threshold voltage. If the erase cell threshold voltage is limited, then the cell current during a "read" operation will be small, which makes sensing the erased or programmed state of the floating gate more difficult. Moreover, the process and circuit parameter variations will greatly reduce the yield of the memory product.